The present invention relates to a power metal-oxide-semiconductor (MOS) device, and in particular, to a power MOS field effect transistor (FET) device having a tungsten plug drain extension.
Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246, the contents of all of which are incorporated herein by reference, are examples of such efforts.
U.S. Pat. No. 6,410,958 (“Usui, et al.”) relates to an edge termination structure and a drift region for a semiconductor component. A semiconductor body of one conductivity type has an edge area with a plurality of regions of the other conductivity type embedded in at least two mutually different planes. Underneath an active zone of the semiconductor component, the drift regions are connected using the underlying substrate. U.S. Pat. No. 6,307,246 (“Nitta, et al.”) discloses a semiconductor component having a high-voltage sustaining edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. U.S. Pat. No. 6,300,171 (“Frisina”) discloses a method for manufacturing an edge structure for a high voltage semiconductor device.
Referring to FIG. 1A, there is shown a partial elevational view of a conventional n-channel planar power MOSFET cell 10. A semiconductor substrate 3 that is part of a semiconductor device that includes a plurality of semiconductor cells 10 and a termination region 100 (see e.g., FIGS. 6-9) all of which are formed on the semiconductor substrate 3. Typically, the semiconductor substrate 3 is formed of silicon (Si). But, the semiconductor substrate 3 may be formed of other materials such as gallium arsenide (GaAs), germanium (Ge) or the like. A voltage sustaining layer 29 is formed on a surface of the semiconductor substrate 3 which includes an upper boundary formed by a heavily doped deep p+ region 13. The voltage sustaining layer 29 extends to a gate oxide layer 11 via a junction field effect transistor (JFET) region 35. The voltage sustaining layer 29 includes an n-doped center region 5 that is surrounded-by a p conductivity region 7 which in turn is surrounded by an oxide or dielectric boundary 9. There is an active zone of the heavily doped deep p+ region 13 on top of the voltage sustaining layer 29 that surrounds the JFET region 35. A heavily doped n+ source terminal region 12 is implanted in the heavily doped deep p+ region 13. The gate oxide layer 11 covers the heavily doped deep p+ region 13, the heavily doped n+ source regions 12, the JFET region 35 and the channel regions 33. A gate terminal 15 is positioned over the gate oxide layer 11. When an appropriate voltage is applied to the gate terminal 15, current conduction is achieved between the n+ source region 12 and the n+ drain that is part of the substrate 3 through channel regions 33. The JFET region 35 reduces undesirable effects from leakage current.
Similarly, a sectional elevational view of a conventional p-channel planar power MOSFET cell 50 is shown in FIG. 1B. A semiconductor substrate 30 that is part of a semiconductor device that includes a plurality of semiconductor cells 50 and termination region 100 (see e.g., FIGS. 6-9) all of which are formed on the semiconductor substrate 30. There is a voltage sustaining layer 229 formed on the substrate 30 which extends from the substrate 30 through an upper boundary formed by a heavily doped deep n+ region 63. The voltage sustaining layer 229 extends to a gate oxide layer 11 via a JFET region 35 as described above. The voltage sustaining layer 229 includes a p-doped center region 21 that is surrounded by an n conductivity region 70 which in turn is surrounded by an oxide or dielectric boundary 9. There is an active zone of the heavily doped deep n+ region 63 on top of the voltage sustaining layer 229 that surrounds the JFET region 35. A heavily doped p+ source terminal region 62 is implanted in the heavily doped deep n+ region 63. A gate oxide layer 11 covers the heavily doped deep n+ region 63, the heavily doped p+ source regions 62, the JFET region 35 and channel regions 33. A gate terminal 15 is positioned over the oxide layer 11 so that when an appropriate voltage is applied to the terminal 15 current conduction is achieved between the p+ source region 62 and the p+ drain that is part of the substrate 30 through channel regions 33. The JFET region 35 reduces undesirable effects from leakage current.
FIG. 2A is a partial top plan view of a conventional planar power MOSFET of the type described above having a frame geometry. FIG. 2B is a partial top plan view of a conventional planar power MOSFET of the type described above having an interdigitated geometry.
It is desirable to provide a method of manufacturing a superjunction semiconductor device having a tungsten plug drain extension, as well as the resultant device formed therefrom.